At a Glance
Sunday, October 2 |
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| 15:30 — 19:00 |
Registration |
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Monday, October 3 |
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| 8:15 |
Registration | ||
| 8:45 Room I.4 |
Welcome |
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| 9:00 Room I.4 |
Keynote: Designing Phase-Locked Loops in Modern CMOS Technologies |
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| 10:00 — 11:40 | M1A — Room II.8 | Systems on Chip Session chair: Prof. Dimitrios Soudris, NTUA |
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| Embedded TCP/IP Controller for a RISC-V SoC — full text — slides— video | Chun-Jen Tsai and Yi-De Lee | ||
| A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs — full text — slides | Alexander Fusco, Sahil Hassan, Joshua Mack and Ali Akoglu | ||
| RISC-V Processor Trace Encoder with Multiple Instructions Retirement Support — full text — slides— video | Halil Kükner, Gökhan Kaplayan, Ahmet Efe and Mehmet Ali Gülden | ||
| RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC — full text — slides | Akshay Sarman, Alwin Shaju, Rose George Kunthara, Neethu K, Rekha K. James and John Jose | ||
| M1B — Room II.9 | Design Automation – 1 Session chair: Dr. Victor Grimblatt, Synopsys |
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| Guiding FPGA Detailed Placement Via Reinforcement Learning — full text — slides— video | Pooria Esmaeili, Timothy Martin, Shawki Areibi and Gary Grewal | ||
| Generation of Formal CPU Profiles for Embedded Systems — full text — slides | Stian Sorensen, Christian Bartsch, Dominik Stoffel and Wolfgang Kunz | ||
| Simulation-Based Maximum Coverage Hazards Detection and Elimination Analysis, Supporting Combinational Logic Loops — full text — slides | Nikolaos Chatzivangelis, Dimitris Valiantzas, Christos Sotiriou and Iordanis Lilitsis | ||
| Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows — full text — slides | Nikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Christos Sotiriou and Evangelos Bakas | ||
| Break |
| 12:00 — 13:30 | SS1 — Room II.8 | Special Session on Computation-in-Memory: Opportunities and challenges Organizer: Prof. Said Hamdioui, Delft University of Technology |
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| FeFET versus DRAM based PIM Architectures: A Comparative Study — full text — slides | Chirag Sudarshan, Taha Soliman, Thomas Kämpfe, Christian Weis and Norbert Wehn | ||
| Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing — full text | Shubham Kumar, Swetaki Chatterjee, Simon Thomann, Paul R. Genssler, Yogesh Singh Chauhan and Hussam Amrouch | ||
| System Design for Computation-in-Memory: From Primitive to Complex Functions — full text — slides | Mahdi Zahedi, Taha Shahroodi, Abhairaj Singh, Geert Custers, Stephan Wong and Said Hamdioui | ||
| SS2 — Room II.9 | Special Session on Front-end circuits and subsystems for 5G applications Organizer: Prof. Grigorios Kalivas, Univ. of Patras |
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| A Wideband High-Gain Power Amplifier Operating in the D Band — full text — | Vasileios Manouras and Ioannis Papananos | ||
| Frequency Synthesizers for 5G Applications — full text | Salvatore Levantino | ||
| 30 GHz Front-End with Adaptively Biased PA and Current Steering LNA for Phased Array Systems — full text | Panagiotis Gkoutis, Georgios Konidas and Grigorios Kalivas | ||
| 11:40 — 13:30 | *Poster 1:Design and Applications Session chair: Prof. Paris Kitsos |
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| Lunch |
| 14:45 — 16:25 | M2A — Room II.8 | Digital Design Session chair: Prof. Ibrahim Elfadel, Khalifa University |
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| An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing — full text — slides | Michael Keyser, Roman Gauchi and Pierre-Emmanuel Gaillardon | ||
| A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency — full text— slides | Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas and Bevan Baas | ||
| Exploring Approximate Comparator Circuits on Power Efficient Design of Decision Trees — full text — slides | Pedro Silva, Mateus Grellert and Cristina Meinhardt | ||
| M2B — Room II.9 | Design Automation – 2 Session chair: Prof. Christos Sotiriou, Univ. of Thessaly |
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| Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography — full text — slides— video | Kritanta Saha, Pritha Banerjee and Susmita Sur-Kolay | ||
| SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-stage Partition — full text — slides— video | Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu and Ting-Chi Wang | ||
| FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory — full text — slides — video | Christopher Chuvalas and Ranga Vemuri | ||
| LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction– full text — slides— video | Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu and Ting-Chi Wang | ||
| Break |
| 16:45 — 18:25 | M3A — Room II.8 | Analog Design Session chair: Prof. Costas Psychalinos, University of Patras |
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| Machine Learning based Power Converter Large Signal Simulation for Energy Harvesting Applications –– full text – slides | George Vergos, Vasiliki Gogolou, Christina Panagiotopoulou, Anastasios Avgoustidis, Thomas Noulis, Kostas Siozios and Stylianos Siskos | ||
| A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAM — full text — slides | Jose Cayo, Ioannis Vourkas and Antonio Rubio | ||
| A novel wide frequency range 65nm CMOS VCO– full text – slides | Dimitrios Samaras, Andreas Tsimpos and Alkis Hatzopoulos | ||
| A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology– full text – slides | Manasa Madhvaraj, Salvador Mir and Manuel J. Barragan | ||
| M3B — Room II.9 | Circuits for Communications Session chair: Prof. Fatih Ugurdag, Ozyegin University |
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| Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder– full text— slides | Renjie Chen, Aaron Stillmaker and Bevan Baas | ||
| High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS– full text – slides— video | Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Jesus Gutiérrez, Milos Krstic and Eckhard Grass | ||
| A FPGA implementation of the VESA Display Stream Compression decoder– full text – slides | Nikolaos Kefalas and George Theodoridis | ||
| High-Level Synthesis design approach for Number-Theoretic Multiplier– full text – slides | Islam Aleaxnder El-Kady, Apostolos Fournaris and Vassilis Paliouras | ||
| *Papers in session Poster 1: Design and Applications Room II.3 Session chair: Prof. Paris Kitsos, University of Peloponnese |
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| Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge — full text | Ashwin Bhat, Adou Sangbone Assoa and Arijit Raychowdhury | ||
| ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches — full text | Yogesh Kumar, S Sivakumar and John Jose | ||
| Flexible Security and Privacy, System Architecture for IoT, in Healthcare — full text | Kyriaki Tsantikidou and Nicolas Sklavos | ||
| Enabling Automotive Electrification on Heterogeneous Automotive Microcontroller using Virtual System Modelling — full text | Rupali Hongekar, Ankita Gupta, Jayakrishna Guddeti and Meghashyam Ashwathnarayan | ||
| A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking — full text | Raiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J and Sneh Saurabh | ||
| Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking — full text | Anastasios Michailidis, Thomas Noulis and Kostas Siozios | ||
| Practical Day-Ahead Power Prediction of Solar Energy-Harvesting for IoT Systems — full text | Konstantinos Falis, Andreas Tsiougkos and Vasilis F. Pavlidis | ||
| Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications — full text | Kamalika Datta, Saman Froehlich, Dev Narayan Yadav, Saeideh Shirinzadeh, Indranil Sengupta and Rolf Drechsler | ||
| A Power Reduction Technique Based on Linear Transformations for Cryptographic Block Ciphers — full text | Elif Bilge Kavun | ||
| Run Time Power and Accuracy Management with Approximate Circuits — full text | Nahla El-Araby, David Frismuth, Nilson Neves Filho and Axel Jantsch | ||
| Efficient Dynamic Logic Magnitude Comparators — full text | Constantinos Efstathiou, Laura Agalioti and Yiorgos Tsiatouhas | ||
| Power Analysis Attack on Locking SIB based IJTAG Achitecture — full text | Gaurav Kumar, Anjum Riaz, Yamuna Prasad and Satyadev Ahlawat | ||
| Hardware Trojan Mitigation for Securing On-chip Networks from Dead Flit Attacks — full text | Mohammad Humam Khan, Ruchika Gupta, Vedika J. Kulkarni, John Jose and Sukumar Nandi | ||
Tuesday, October 4 |
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| 8:15 |
Registration |
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| 8:45 – Room I.4 |
Keynote: Preserving Design Hierarchy Information for Polynomial Formal Verification — invited paper, |
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| 9:45 — 11:25 | T1A — Room II.8 | Fault tolerance and testing Session chair: Prof. Nicolas Sklavos, University of Patras |
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| Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space — full text — slides | Vasileios Leon, Elissaios Alexios Papatheofanous, George Lentaris, Charalampos Bezaitis, Nikolaos Mastorakis, Georgios Bampilis, Dionysios Reisis and Dimitrios Soudris | ||
| Fast and accurate Model-Driven FPGA-based System-Level Fault Emulation— full text — slides | Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz and Wolfgang Ecker | ||
| A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip Designs— full text— slides– video | Anu Asokan | ||
| T1B — Room II.9 | Modelling Session chair: Prof. Graziano Pravadelli, University of Verona |
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| A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms— full text — slides | Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis and Nikolaos Voros | ||
| MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge— full text — slides | Theo Soriano, David Novo, Guillaume Prenat, Gregory Di Pendina and Pascal Benoit | ||
| NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool— full text — slides | Nils Bosbach, Lukas Jünger, Jan Moritz Joseph and Rainer Leupers | ||
| Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions— full text — slides | Samuele Germiniani and Graziano Pravadelli | ||
| 9:45 — 11:25 | **Poster 2: Student forum | ||
| Break |
| 11:45 — 13:30 | SS3 — Room II.8 | Special Session on Variability in ReRAM devices: mitigation and opportunities for exploitation Organizers: Prof. Ioannis Vourkas, Federico Santa Maria Technical University, Prof. Georgios Ch. Sirakoulis, Democritus University of Thrace, Prof. Antonio Rubio, Polytechnic University of Catalonia |
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| End-to-end modelling of variability-aware neural networks based on resistive-switching memory arrays — full text — slides | Artem Glukhov, Nicola Lepri, Valerio Milo, Andrea Baroni, Cristian Zambelli, Piero Olivo, Eduardo Pérez, Christian Wenger and Daniele Ielmini | ||
| Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM — full text — slides | Carlos Fernandez and Ioannis Vourkas | ||
| Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs — full text — slides | Anteneh Gebregiorgis, Abhairaj Singh, Sumit Diware, Rajendra Bishnoi and Said Hamdioui | ||
| Substrate Effect on Low-frequency Noise of synaptic RRAM devices — full text — slides | Nikolaos Vasileiadis, Alexandros Mavropoulis, Panagiotis Loukas, Pascal Normand, Georgios Ch. Sirakoulis and Panagiotis Dimitrakis | ||
| SS4 — II.9 | Special Session on Computing Circuits and SoCs for Space Applications Organizer: Prof. Dionysios Reisis, National and Kapodistrian University of Athens |
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| SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite Images — full text — slides | Elissaios Alexios Papatheofanous, Philippos Tziolos, Vasileios Kalekis, Tzouma Amrou, Georgios Konstantoulakis, Georgios Venitourakis and Dionysios Reisis | ||
| Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications — full text — slides | Vasileios Leon, George Lentaris, Dimitrios Soudris, Simon Vellas and Mathieu Bernou | ||
| A low-power, radiation-hardened Single Event Effect rate detection System on a Chip for Real Time Monitoring of Single Event Effects on Low Earth Orbit satellites — full text — slides | Georgios Kottaras, Theodoros Sarris, Athanasios Psomoulis, Ilias Ioakeimidis, Angelos Papathanasiou, Dave Pitchford and Ingmar Sandberg | ||
| High-Performance Hardware Accelerators for Next Generation On-Board Data Processing — full text — slides | Antonios Paschalis and Nektarios Kranitis | ||
| 11:40 — 13:30 | ***Poster 3:Phd Forum | ||
| Lunch |
| Social program: Visit to Olympia |
| Social program: Gala Dinner |
| **Papers in Session Poster 2: Student Forum Room II.3 Organizers/co-chairs: Prof. Ricardo Reis, UFRGS, Prof. Alexandra Lackmann Zimpeck, UFRGS, Prof. Ioannis Kouretas, University of Patras |
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| Assessing IMD of a Direct-to-RF Platform — full text | Jonathan Merk, Changhai Lin and Matthias Kamuf | |||
| Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors — full text | Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O’Connor, Oskar Baumgartner and David Pirker | |||
| On the Design and Development of a ReRAM-based Computational Memory Prototype — full text | Carlos Fernandez and Ioannis Vourkas | |||
| A 18-27 GHz Programmable Gain Amplifier in 65-nm CMOS technology — full text | Carolina del Río Bueno, Uxua Esteban Eraso, Santiago Celma Pueyo and Carlos Sánchez-Azqueta | |||
| Modeling frequency response of gm-boosted inductorless Common-Gate LNA — full text | Jorge Marqués-García, Alberto Arcusa-Puente, Antonio D. Martínez-Pérez and Francisco Aznar | |||
| Approximation Workflow for Energy-Efficient Comparators in Decision Tree Applications — full text | Pedro Silva, Mateus Grellert and Cristina Meinhardt | |||
| Design and characterisation of a Physically Unclonable Function on FPGA using second-order compensated measurement — full text | Jorge Fernandez-Aragon, Guillermo Diez-Senorans, Miguel Garcia-Bosque and Santiago Celma | |||
| ***Papers in Session Poster 3: PhD Forum Room II.3 Organizers/co-chairs: Prof. Ricardo Reis, UFRGS, Prof. Alexandra Lackmann Zimpeck, UFRGS, Prof. Ioannis Kouretas, University of Patras |
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| Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devices — full text | Jonas Gava, Ricardo Reis and Luciano Ost | |||
| Systematic Embedded Development and Implementation Techniques on Intel Myriad VPUs — full text | Vasileios Leon, Kiamal Pekmestzi and Dimitrios Soudris | |||
| Architectural Support for Functional Programming — full text | Cecil Accetti and Peilin Liu | |||
| Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity — full text | Foroozan Karimzadeh and Arijit Raychowdhury | |||
| Speculative guardband: exploiting critical-delay variations across cached instructions — full text | Johannes Warwick Farias, Diego V. C. Nascimento, Tiago Barros and Samuel Xavier-de-Sousa | |||
| Routability-Driven Detailed Placement Using Reinforcement Learning — full text | Sheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat and Cristina Meinhardt | |||
| Analog Compute in Memory and Breaking Digital Number Representations — full text | Nathan Laubeuf | |||
| A CMOS 4-bit Digitally Programmable Phase Shifter for the K-band — full text | Uxua Esteban Eraso, Carlos Sánchez-Azqueta, Concepción Aldea and Santiago Celma | |||
| Automated Framework for Fast Synthesis of Approximate Hardware Accelerators — full text | Muhammad Awais and Marco Platzner | |||
| Exploring Approximate Computing Approaches to Design Power-efficient Multipliers — full text | Vinícius Zanandrea and Cristina Meinhardt | |||
Wednesday, October 5 |
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| 8:15 |
Registration | ||
| 8:45 Room I.4 |
Keynote:Challenges in Hardware Implementations of Fully Homomorphic Encryption Algorithms |
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| 9:45 — 11:25 | W1A — Room II.8 | Artificial Intelligence and Machine Learning – 1 Session chair: Prof. George Theodoridis, University of Patras |
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| P2M-DeTrack: Processing-in-Pixel-in-Memory for Real-Time and Energy-Efficient Multi-Object Detection and Tracking –– full text — slides | Gourav Datta, Souvik Kundu, Zihan Yin, Joe Mathai, Zeyu Liu, Zixu Wang, Mulin Tian, Shunlin Lu, Ravi T. Lakkireddy, Andrew Schmidt, Wael Abd-Almageed, Ajey P. Jacob, Akhilesh R. Jaiswal and Peter A. Beerel | ||
| Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge Distillation — full text — slides— video | Foroozan Karimzadeh and Arijit Raychowdhury | ||
| Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM) — full text — slides | Asmae El Arrassi, Anteneh Gebregiorgis, Anass El Haddadi and Said Hamdioui | ||
| High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite Images — full text — slides | Konstantina Koliogeorgi, Dimitris Mylonakis, Sotirios Xydis and Dimitrios Soudris | ||
| W1B — Room II.9 | Hardware for security Session chair: Dr. Apostolos Fournaris, ISI |
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| PA-PUF: A Novel Priority Arbiter PUF — full text — slides | Simranjeet Singh, Srinivasu Bodapati, Sachin Patkar, Rainer Leupers, Anupam Chattopadhyay and Farhad Merchant | ||
| Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection — full text — slides | Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz and Wolfgang Ecker | ||
| Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers — full text — slides | Can Aknesil and Elena Dubrova | ||
| Logic Locking of Finite-State Machines Using Transition Obfuscation — full text — slides | Shahzad Muzaffar and Ibrahim Elfadel | ||
| Break |
| 11:45 — 13:25 | W2A — Room II.8 | Artificial Intelligence and Machine Learning – 2 Session chair: Prof. Lech Józwiak, Eindhoven University of Technology |
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| ZaLoBI: Zero avoiding Load Balanced Inference accelerator — full text — video | Imlijungla Longchar, Palash Das and Hemangee K. Kapoor | ||
| Toward Large Scale All-Optical Spiking Neural Networks — full text — slides | Milad Eslaminia and Sébastien Le Beux | ||
| FPGA-SoC deployment of complex deep neural network for magnitude and phase computations in denoising of speech signal — full text — slides | Georgios Flamis, Stavros Kalapothas and Paris Kitsos | ||
| Confidential Inference in Decision Trees: FPGA Design and Implementation — full text — slides | Rupesh Karn and Ibrahim Elfadel | ||
| SS5 — Room II.9 | Special Session on Key enabling technologies for the physical-layer of 6G communications Organizer: Dr. Evangelos Vlachos, Industrial Systems Institute |
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| Secrecy spectral efficiency optimization in RIS-enabled MIMO Communication Systems — full text— slides | Konstantinos D. Katsanos and George C. Alexadropoulos | ||
| Accurate real-time UAV flight-mode classification — full text — slides | Nikolaos Georgiou and Panayiotis Kolios | ||
| Quantum computing-assisted Channel Estimation for Millimeter-Wave Massive MIMO Communications — full text — slides | Evangelos Vlachos and Kostas Blekos | ||
| Awards and farewell |
| Lunch |